1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device which enables storing analog information and multiple-valued information using memory cell transistors having floating gates.
2. Description of the Related Art
In an electrically erasable programmable ROM (EEPROM) in which a memory cell is composed of a single transistor, each memory cell is formed by a double gate transistor having a floating gate and a control gate. In such a double gate memory cell transistor, data are written to the memory cell transistor by accelerating and injecting hot electrons generated on the drain region side of the floating gate. On the other hand, data are read out from the memory cell transistor by detecting a difference in performance characteristics of the memory cell transistor which may arise depending on whether or not electric charges are injected into the floating gate.
FIG. 1 is a top view of the memory cell portion of a nonvolatile semiconductor memory device having floating gates, and FIG. 2 is a sectional view along its X--X line. These drawings show split gate structure in which a part of a control gate is arranged side by side with a floating gate.
On the surface area of a P-type silicon substrate 1, a plurality of isolated regions 2 composed of oxide film (LOCOS), which is thickly formed in selective, are formed in rectangular pattern, and element regions are marked off by the oxide film (LOCOS). On the oxide film 3 formed on the silicon substrate 1, a plurality of floating gates 4 are arranged such that each of these gates stretches over two neighboring isolated regions 2. The floating gates 4 are independently arranged at every memory cell. Further, oxide film 3a is thickly formed on the central part of each of the floating gates 4, thereby causing the edge of the respective floating gates 4 to form an acute angle. This facilitates electric field enhancement at the edge of the respective floating gates 4 when data is erased. On the silicon substrate 1 where a plurality of floating gates 4 are arranged, control gates 5 are arranged in such a manner that each control gate 5 corresponds to the floating gate 4 in every row. These control gates 5 are arranged in such a manner that a portion of each control gate 5 lies on the oxide film 3a and faces the corresponding floating gates 4 and the remaining part lies upon the oxide film 3 and faces the silicon substrate 1. These floating gates 4 and control gates 5 are arranged in such a manner that the respective neighboring rows have a plane symmetry with each other. In a substrate region between neighboring control gates 5 and a substrate region between neighboring floating gates 4, N-type first diffusion layers 6d and second diffusion layers 6s are formed. Each of the first diffusion layers 6d is surrounded by the isolated region 2 between neighboring control gates 5 and is thereby independent. The second diffusion layers 6s are arranged between neighboring floating gates 4 successively in a direction which the control gates 5 are extended. A memory cell transistor is composed of one floating gate 4, one control gate 5, one first diffusion layer 6d, and one second diffusion layer 6s. Here, the first diffusion layer 6d becomes a drain, whereas the second diffusion layer 6s becomes a source. On the oxide film 7 formed on each control gate 5, aluminum wiring 8 is arranged in a direction which the aluminum wiring 8 intersects the control gates 5. The aluminum wiring 8 is connected to the first diffusion layers 6d through contact holes 9.
For a memory cell transistor having such double gate structure, an ON-state resistance value between the source and the drain fluctuates with the amount of electric charge injected into the floating gate 4. Thus, by selectively injecting into the floating gate 4 an amount of electric charge which is in proportion to memory information, an ON-state resistance value of specified memory cell transistor may be varied in multiple stages.
FIG. 3 is a circuit diagram of the memory cells portion shown in FIG. 1. This diagram shows memory cells arranged in four rows of four.
In memory cell transistors 11 having a double gate structure, the control gates 5 arranged in the same row are connected to one of the word lines 12, and the first diffusion layers 6d (drains) arranged in the same column are connected to one of the bit lines 13 while the second diffusion layers 6s (sources) are connected to source line 14. The respective bit lines 13 are connected to a data line 16 via selection transistors 15 and also connected to a sense amplifier (not shown in drawings) to read out a voltage value.
The source line 14 to which each row of the memory cell transistors 11 is connected in common provides a write clock having a regular cycle .phi.W to each of the memory cell transistors 11. Further, the data line 16, which is selectively connected to each of the bit lines 13 via each of the selection transistors 15, selectively provides a read clock .phi.R to each of the memory cell transistors 11. In the case of an ordinary device, the respective control gates 5 which are formed at the same row of the memory cell transistors 11 in common are used as word lines 12, whereas the aluminum wirings 8 to be connected with the first diffusion layers 6d are used as bit lines 13. Further, the second diffusion layers 6s extended in parallel with the control gates 5 are used as source lines 14.
Row selection signals LS1 to LS4 are generated based on row address information. By selecting one of the word lines 12, a specified row of the memory cell transistors 11 is activated. Column selection signals CS1 to CS4 are generated based on column address information. By turning on one of the selection transistors 15, a specified column of the memory cell transistors 11 is activated. Thus, one of the plurality of memory cell transistors 11 to be arranged in a queue is designated based on the row address and column address information, and connected to the data line 16.
When data are written into one of the memory cell transistors 11, an earth potential (for example, 0V) is applied from one of the bit lines to the memory cell transistor 11, and a write potential (for example, 14V) is applied thereto from the source line 14. Thus, data are written into a specified memory cell transistor 11 which is selected in response to the row selection signals LS1 to LS4 and the column selection signals CS1 to CS4. In other word, electric charges are injected into the floating gate 4 of a specified memory cell. Further, when the data written into the memory cell transistor 11 are read out, a read potential (for example, 5V) is applied from one of the bit lines 13 and an earth potential (for example, 0V) is applied from the source line 14 to the memory cell transistor 11, respectively. Current then flows through the selected memory cell transistor 11 and a potential of the bit lines 13 fluctuates according to an ON-state resistance value of the memory cell transistor 11. The potential of the bit line at this time can be read out by the sense amplifier.
When analog information is written into the memory cell transistor 11, injection of electric charges (writing of data) and confirmation of the amount of the injection (reading of data) are repeated at a short interval in order to enhance recording accuracy. More specifically, while data are written into the memory cell transistor 11 little by little, all data are read out each time. When contents of the data to be stored coincides with the result of reading out, writing is terminated. For example, as shown in FIG. 4, write clock .phi.W and read clock .phi.R are set in reverse phase to each other, and either a write potential and a read potential or an earth potential are alternately applied to the bit lines 13 selected and source line 14 at regular intervals. Thus, the write clock .phi.W is raised and a write potential is applied to the source line 14, whereby a period of applying an earth potential to the bit line 13 becomes a writing period W. Further, the read clock .phi.R is raised and a read potential is applied to the selected bit lines 13, whereby a period of applying an earth potential to the source line 14 becomes a reading period R. When the result of reading out reaches a desired potential corresponding to memory information in reading operation, the write clock .phi.W is terminated and writing operation completes.
FIG. 5 is a block diagram showing the constitution of a sense amplifier to detect an ON-state resistance value of the memory cell transistor 11 which is connected to the bit line 13.
The sense amplifier is composed of a pair of load resistances 21 and 22, a pair of current amplifiers 23 and 24, a reference transistor 25, a controlled potential generating circuit 26, a differential amplifier 27, and a determination control circuit 28. The pair of load resistances 21 and 22 have the same resistance value and are connected to a power source. The pair of current amplifiers 23 and 24 are composed of transistors and inverters, and are connected to the pair of load resistances 21 and 22 connected to the power source. The bit line 13 to be connected to the memory cell transistor 11 is connected to the current amplifier 23 on one side, whereas the reference transistor 25 is connected to the current amplifier 24 on the other side. The reference transistor 25 is connected between the current amplifier 24 and an earth point, and varies a resistance value in response to a reference potential VRG which is applied to a gate of the reference transistor 25. The controlled potential generating circuit 26 generates the reference potential VRG which is corresponding to multiple-valued information to be stored in the memory cell transistor 11, and then provides the reference potential VRG to a gate of the reference transistor 25. For example, when the memory cell transistor 11 stores information of four values (two-bit portions), three kinds of gate potentials VRG are successively generated so as to vary the resistance value of the reference transistor 25 in three stages.
Two inputs of the differential amplifier 27 are connected to contact points with both the pair of load resistances 21 and 22 and the pair of current amplifiers 23 and 24. The differential amplifier 27 compares potentials VBL and VRL of each contact point, and provides a comparison output CO to a determination control circuit 28. The determination control circuit 28 controls generation of the reference potential VRG by the controlled potential generating circuit 26. It also discriminates the comparison output CO provided from the differential amplifier 27 and generates data D1 and D2 of multiple bits corresponding to multiple-valued information. For example, when information of four values is discriminated, the intermediate reference potential among three levels of reference potentials is first generated in order to determine a superior bit, and then either of higher and lower potentials among the three levels of reference potentials is generated according to the result of determination of the superior bit in order to determine an inferior bit.
When data are read out from the memory cell transistor 11, as the source of the memory cell transistor 11 is grounded, the load resistance 21 and the memory cell transistor 11 are connected in series between a power supply and an earth via the current amplifier 23. Similarly, the load resistance 22 and the reference transistor 25 are connected in series between a power supply and an earth via the current amplifier 24. A potential VBL at the contact point of the load resistance 21 and the current amplifier 23 is determined based on a ratio of the load resistance 21 to the memory cell transistor 11 in driving force. Similarly, a potential VRL at the contact point of the load resistance 22 and the current amplifier 24 is determined based on a ratio of the load resistance 22 to the reference transistor 25 in driving force. Therefore, based on the comparison output CO from the differential amplifier 27, it is possible to determine a range in which a resistance value of the memory cell transistor 11 is, as compared with the reference transistor 25 whose resistance value is varied in stages. Such a sense amplifier is, for example, disclosed in 1995 IEEE/International Solid-State Circuit Conference/Session 7/Flash Memory/Paper TA 7.7.
In the case of a split gate type memory cell transistor 11, whenever writing is performed by the write clock .phi.W (electric charges are injected into the floating gate), an ON-state resistance value becomes high. Therefore, at the time of reading operation which is alternately repeated with writing operation, a potential VBL of the bit line 13 varies in stages from an earth potential to a power supply potential as the writing operation is repeated, as shown in FIG. 6. A variation of the potential VBL at the bit line 13 resulting from the writing operation performed once is large in the beginning of the writing operation, but gradually becomes small with the progress of the writing operation. Further, when it finally reaches the power supply potential VDD, the potential VBL at the bit line 13 no longer varies.
When the memory cell transistor 11 is made to store multiple-valued information, a range between the earth potential and the power supply potential is equably divided by the number of steps of memory information, and the number of writing operations is controlled in order that the bit line potential VBL at the time of a reading operation corresponds to one of the divided potentials to be written. For example, as described above, when the memory cell transistor 11 is made to store information of four values, for the purpose of enabling reading out two kinds of intermediate values, the number of writing operations is controlled so that the bit line potential VBL coincides with either of the potentials VDD/3 or 2VDD/3 which are two parts of a trisection of the power supply potential VDD (the earth potential is 0V). However, if an amount of electric charges in writing operation at a time is large, in other words, if a rate of change of the bit line potential VBL is large (a sharp rise of the curved line shown in FIG. 6), it will be difficult to accurately control the bit line potential VBL and therefore there will be a large error in the values between a desired potential to be written and a bit line potential VBL to be read out. Consequently, resolution of the memory cell transistor 11 is deteriorated, thereby making it difficult to achieve a multiplicity of values of memory information.